1. Field of the Invention
This invention relates to semiconductor devices and more particularly to MOSFET memory devices and methods of manufacture thereof.
2. Description of Related Art
U.S. Pat. No. 5,103,274 of Tang et al. for "Self-Aligned Source Process and Apparatus" and shows a method and apparatus for self-aligning a source region with a field oxide region and a polysilicon gate and word line in a semiconductor device.
U.S. Pat. No. 5,120,671 of Tang et al. for "Process for Self Aligning a Source Region with a Field Oxide Region and a Polysilicon Gate" teaches a method and apparatus for self-aligning a source region with a field oxide region and a polysilicon gate and word line in a semiconductor device. The method and apparatus allows reduced memory cell size and improved device density by substantially eliminating the bird's beak encroachment and corner rounding effects usually found between neighboring cells due to inadequacies in the prior art photolithography process.
U.S. Pat. No. 5,534,455 of Liu for "Method for Protecting a Stacked Gate Edge in a Semiconductor Device from Self Aligned Source (SAS) Etch" shows a process for protecting the stacked gate edge of a semiconductor device. The process provides the step of spacer formation before the Self-Aligned Source (SAS) etching is accomplished.